Senior/Staff Front-End Engineer (SOC)

Implement Verilog RTL for various sections of SoC.

Work with IP engineers to integrate IPs to the SoC.

Support synthesis, timing closure, power reduction, and floorplanning efforts to optimize performance and efficiency.

Contribute to design verification & emulation and assist in debugging issues across pre-silicon and post-silicon stages.

Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering or Computer Engineering with 5 years or more in a semiconductor or high technology R&D experience would be appreciated.

Verilog RTL development experience with industry-standard tools in an SoC environment.

Strong understanding of SoC architecture and logic design.

Strong problem-solving and debugging skills.

Knowledge of clocking, reset sequences, power-up sequences, and power management.

Exposure to verification methods.

Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks.

Knowledge of emulation and FPGA prototyping is preferred.

A culture that values authenticity and diversity of thoughts and backgrounds;

An inclusive and respectable environment with open workspaces and exciting start-up spirit;

Fast-growing company with the chance to network with industrial pioneers and enthusiasts;

Ability to contribute directly and make an impact on the future of the digital asset industry;

Involvement in new projects, developing processes/systems;

Personal accountability, autonomy, fast growth, and learning opportunities;

Attractive welfare benefits and developmental opportunities such as training and mentoring.